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| M Features * * * * * * * * Low Quiescent Current: 600 nA/Amplifier (typ.) Stable for gains of 10 V/V or higher Rail-to-Rail Input: -0.3V (min.) to VDD + 0.3V (max.) Rail-to-Rail Output: - VSS+10 mV (min.) to V DD-10 mV (max.) Gain Bandwidth Product: 100 kHz (typ.) Wide Supply Voltage Range: 1.4V to 5.5V (max.) Available in Single, Dual and Quad Chip Select (CS) with MCP6143 MCP6141/2/3/4 Description The MCP6141/2/3/4 family of non-unity gain stable operational amplifiers (op amps) from Microchip Technology, Inc. operate with a single supply voltage as low as 1.4V, while drawing less than 1 A (max.) of quiescent current per amplifier. These devices are also designed to support rail-to-rail input and output swing. The MCP6141/2/3/4 op amps have a gain bandwidth product of 100 kHz (typ.) and are stable for gains of 10 V/V or higher. This specification makes these devices appropriate for battery-powered applications where higher frequency responses from the amplifier are required. The MCP6141/2/3/4 family of op amps are offered in single (MCP6141), single with a Chip Select (CS) feature (MCP6143), dual (MCP6142) and quad (MCP6144) configurations. 600 nA, Non-Unity Gain Rail-to-Rail Input/Output Op Amps Applications * * * * Toll Booth Tags Wearable Products Temperature Measurement Battery-Powered Available Tools * Spice macro models (at www.microchip.com) * FilterLab(R) Software (at www.microchip.com) Typical Applications VDD VDD Package Types MCP6141 PDIP, SOIC, MSOP NC 1 -IN 2 +IN 3 VSS 4 + 8 NC 7 VDD 6 OUT 5 NC MCP6142 PDIP, SOIC, MSOP OUTA 1 -INA 2 +INA 3 VSS 4 - A+ +B 8 VDD 7 OUTB 6 -INB 5 +INB 1k +1.4V to 5.5V IDD RI 100 k MCP614X VSS RF = 1 M High Side Battery Current Sensor RF G n = 1 + ------ 10V/V RI V1 V2 V3 R1 R2 R3 I1 I2 I3 RF IF VOUT MCP6143 PDIP, SOIC, MSOP NC 1 -IN 2 +IN 3 VSS 4 + 8 CS 7 VDD 6 OUT 5 NC MCP6144 PDIP, SOIC, TSSOP OUTA 1 +INA1 3 VDD 4 +INB 5 -INB 6 - B+ + C OUTB1 7 14 OUTD AD -INA1 2 - + + - 13 -IND 12 +IND 11 VSS 10 +INC 9 -INC 8 OUTC VREF MCP614X Summing Amplifier 1 1 1 G n = 1 + R F ----- + ----- + ----- 10V/V R 1 R 2 R 3 2002 Microchip Technology Inc. 21668A-page 1 MCP6141/2/3/4 1.0 1.1 ELECTRICAL CHARACTERISTICS Maximum Ratings PIN FUNCTION TABLE Name +IN/+INA/+INB/+INC/+IND -IN/-INA/-INB/-INC/-IND VDD VSS CS NC Function Non-inverting Inputs Inverting Inputs Positive Power Supply Negative Power Supply Chip Select No internal connection VDD - VSS .........................................................................7.0V All inputs and outputs........................ VSS -0.3V to V DD +0.3V Difference Input voltage ....................................... |VDD - VSS| Output Short Circuit Current ..................................continuous Current at Input Pins ....................................................2 mA Current at Output and Supply Pins ............................30 mA Storage temperature .....................................-65C to +150C Junction Temperature, TJ ............................................ +150C ESD protection on all pins (HBM:MM).................. 4 kV:200 V Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. OUT/OUTA/OUTB/OUTC/OUTD Outputs DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, all limits are specified for VDD = +1.4V to +5.5V, VSS = GND, TA = 25C, VCM = VDD/2, R L = 1 M to VDD /2, and VOUT ~ VDD/2. Parameters Sym VOS VOS/T PSRR IB IB IOS ZCM ZDIFF VCMR CMRR Min -3.0 -- 70 -- -- -- -- -- VSS - 0.3 62 60 60 Typ -- 1.5 85 1.0 -- 1.0 1013||6 10 ||6 -- 80 75 80 13 Max +3.0 -- -- -- 100 -- -- -- VDD + 0.3 -- -- -- Units mV V/C dB pA pA pA ||pF ||pF V dB dB dB Conditions VCM = VSS TA= -40C to +85C Input Offset Input Offset Voltage Drift with Temperature Power Supply Rejection Input Bias Current and Impedance Input Bias Current Input Bias Current Over-Temperature Input Offset Current Common Mode Input Impedance Differential Input Impedance TA= -40C to +85C Common Mode Common-Mode Input Range Common-Mode Rejection Ratio VDD = 5V, VCM = -0.3V to 5.3V VDD = 5V, VCM = 2.5V to 5.3V VDD = 5V, VCM = -0.3V to 2.5V RL = 50 k to VDD /2, 100 mV < VOUT < (V DD - 100 mV) RL = 50 k to VDD /2 VOUT = 2.5V, VDD = 5 V Open Loop Gain DC Open Loop Gain (large signal) AOL 95 115 -- dB Output Maximum Output Voltage Swing Output Short Circuit Current VOL, VOH VSS + 10 IO V DD IQ -- 1.4 0.3 -- 21 -- 0.6 VDD - 10 -- 5.5 1.0 mV mA V A IO = 0 Power Supply Supply Voltage Quiescent Current per amplifier 21668A-page 2 2002 Microchip Technology Inc. MCP6141/2/3/4 AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, all limits are specified for VDD = +5V, VSS = GND, TA = 25 C, VCM = VDD/2, R L = 1 M to VDD /2, CL = 60 pF, and VOUT ~ VDD /2. Parameters Gain Bandwidth Product Slew Rate Phase Margin Input Voltage Noise Input Voltage Noise Density Input Current Noise Density Sym GBWP SR PM En en in Min -- -- -- -- -- -- Typ 100 24 60 5.0 170 0.6 Max -- -- -- -- -- -- Units kHz V/ms Vp-p nV/Hz fA/Hz G = +10 f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz Conditions SPECIFICATIONS FOR MCP6143 CHIP SELECT FEATURE Electrical Characteristics: Unless otherwise indicated, all limits are specified for VDD = +1.4V to +5.5V, VSS = GND, TA = 25 C, VCM = VDD/2, R L = 1 M to VDD /2, CL = 60 pF, and VOUT ~ VDD /2. Parameters Sym Min Typ Max Units Conditions CS Low Specifications CS Logic Threshold, Low CS Input Current, Low VIL ICSL VSS -- -- 5.0 VSS + 0.3 -- V pA For entire VDD range CS = VSS CS High Specifications CS Logic Threshold, High CS Input Current, High CS Input High, GND Current Amplifier Output Leakage, CS High VIH ICSH IQ VDD - 0.3 -- -- -- -- 5.0 20 20 V DD -- -- -- V pA pA pA For entire VDD range CS = VDD CS = VDD CS = VDD Dynamic Specifications CS Low to Amplifier Output High Turn-on Time CS High to Amplifier Output High Z Hysteresis tON tOFF VHYST -- -- -- 2.0 10 0.6 50 -- -- ms s V CS low = VSS + 0.3V, G = +1 V/V, VOUT = 0.9 VDD/2 CS high = VDD - 0.3V, G = +1 V/V VOUT = 0.1 VDD/2 VDD = 5V TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, all limits are specified for VDD = +1.4V to +5.5V, VSS = GND. Parameters Symbol TA TA TA JA JA JA JA JA JA Min -40 -40 -65 -- -- -- -- -- -- Typ -- -- -- 85 163 206 70 108 100 Max +85 +125 +150 -- -- -- -- -- -- Units C C C C/W C/W C/W C/W C/W C/W Note 1 Conditions Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-MSOP Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Note 1: The MCP6141/2/3/4 family of op amps operates over this extended range, but with reduced performance. 2002 Microchip Technology Inc. 21668A-page 3 MCP6141/2/3/4 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = +5V, VSS = GND, TA = 25C, VCM = VDD/2, RL = 1 M to VDD/2, CL = 60 pF, and VOUT ~ V DD/2. 16% 14% 12% 10% 8% 6% 4% 2% 0% -3 -2 -1 0 1 2 3 Input Offset Voltage (mV) 35% 30% 25% 20% 15% 10% 5% 0% -10 -5 0 5 10 Input Offset Voltage Drift (V/C) Percentage of Occurrences FIGURE 2-1: Histogram of Input Offset Voltage with VDD = 5.5V. 16% 14% 12% 10% 8% 6% 4% 2% 0% -3 -2 -1 0 1 2 3 Input Offset Voltage (mV) FIGURE 2-4: Histogram of Input Offset Voltage Drift with VDD = 1.4V. 600 Input Offset Voltage (V) Percentage of Occurrences 1200 Samples VDD = 5.5 V 1200 Samples VDD = 1.4 V Percentage of Occurrences 1200 Samples VDD = 1.4 V VDD = 1.4 V 400 200 0 -200 -400 -600 -0.5 TA = +85C TA = +25C TA = -40C 0.0 0.5 1.0 1.5 Common Mode Input Voltage (V) 2.0 FIGURE 2-2: Histogram of Input Offset Voltage with VDD = 1.4V. 35% 30% 25% 20% 15% 10% 5% 0% -10 -5 0 5 10 Input Offset Voltage Drift (V/C) FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage vs. Temperature with VDD = 1.4V. 600 Input Offset Voltage (V) VDD = 5.5 V TA = +85C TA = +25C TA = -40C Percentage of Occurrences 1200 Samples VDD = 5.5 V 400 200 0 -200 -400 -600 -0.5 TA = +85C TA = +25C TA = -40C 0.5 1.5 2.5 3.5 4.5 Common Mode Input Voltage (V) 5.5 FIGURE 2-3: Histogram of Input Offset Voltage Drift with VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage vs. Temperature with VDD = 5.5V. 2002 Microchip Technology Inc. 21668A-page 4 MCP6141/2/3/4 Note: Unless otherwise indicated, VDD = +5V, VSS = GND, TA = 25C, VCM = VDD/2, RL = 1 M to VDD/2, CL = 60 pF, and VOUT ~ V DD/2. Input Bias, Offset Currents (pA) 500 Input Offset Voltage (V) RL = 50 k 450 400 350 300 250 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) VDD = 5.5 V VDD = 1.4 V 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) TA = 85C VDD = 5.5 V Input Bias Current Input Offset Current FIGURE 2-7: Input Offset Voltage vs. Output Voltage vs. Power Supply Voltage. FIGURE 2-10: Input Bias, Offset Currents vs. Common Mode Input Voltage with Temperature = 85C. 300 1,000 Input Noise Voltage Density (nV/ Hz) Eni = 4.7 VP-P, f = 0.1 to 10 Hz eni = 167 nV/ Hz, f = 1 kHz Input Noise Voltage Density (nV/ Hz) 250 200 150 100 50 0 -0.5 f = 1 kHz VDD = 5.0 V 100 0.1 1 10 100 Frequency (Hz) 1000 0.5 1.5 2.5 3.5 4.5 5.5 Common Mode Input Voltage (V) FIGURE 2-8: vs. Frequency. 100 90 CMRR, PSRR (dB) 80 70 60 50 40 30 20 1 Input Noise Voltage Density FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. 100 CMRR, PSRR (dB) 95 90 85 80 75 70 -40 -20 CMRR (VDD = 5.0 V, VCM = -0.3 V to +5.3 V) 0 20 40 60 Ambient Temperature (C) 80 PSRR (VCM = VSS) PSRR- VDD = 5.0 V PSRR+ Referred to Input CMRR 10 100 100 1000 Frequency (Hz) FIGURE 2-9: Common Mode Rejection Ratio, Power Supply Rejection Ratio vs. Frequency. FIGURE 2-12: Common Mode Rejection Ratio, Power Supply Rejection Ratio vs. Ambient Temperature. 2002 Microchip Technology Inc. 21668A-page 5 MCP6141/2/3/4 Note: Unless otherwise indicated, VDD = +5V, VSS = GND, TA = 25C, VCM = VDD/2, RL = 1 M to VDD/2, CL = 60 pF, and VOUT ~ V DD/2. 50 40 30 20 10 0 25 35 45 55 65 75 85 Input Bias Current Input Offset Current VCM = VDD VDD = 5.5 V Quiescent Current per amplifier (mA) Input Bias and Offset Currents (pA) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 TA = 85C TA = 25C TA = -40C Ambient Temperature (C) Power Supply Voltage (V) FIGURE 2-13: Input Bias and Offset Currents vs. Ambient Temperature. 120 Open-Loop Gain (dB) 100 80 60 40 20 0 -20 0.01 VDD = 5.5 V 10k 10000 100k 100000 1k 1000 10 100 0.1 1 Phase Gain 0 Open-Loop Phase () FIGURE 2-16: Quiescent Current Vs. Power Supply Voltage vs. Temperature. 140 DC Open-Loop Gain (dB) 130 120 110 100 90 80 70 60 100 1k 10k Load Resistance ( ) 100k VDD = 1.4 V VOUT = 0.5 V to 0.9 V VDD = 5.5 V VOUT = 0.5 V to 5.0 V -30 -60 -90 -120 -150 -180 -210 Frequency (Hz) FIGURE 2-14: Open Loop Gain, Phase vs. Frequency with VDD = 5.5V. 140 DC Open Loop Gain (dB) 130 120 110 100 90 80 70 60 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Power Supply Voltage (V) 5.0 5.5 RL = 50 k VOUT = 100 mV to VDD - 100 mV FIGURE 2-17: DC Open Loop Gain vs. Load Resistance vs. Power Supply Voltage. Small Signal DC Open Loop Gain (dB) 140 130 120 110 100 90 80 70 60 0.00 0.05 0.10 0.15 0.20 0.25 0.30 RL = 50 k VDD = 5.5 V VDD = 1.4 V Output Voltage Headroom; VDD-VOUT or VOUT-VSS (V) FIGURE 2-15: DC Open Loop Gain vs. Power Supply Voltage. FIGURE 2-18: Small Signal DC Open Loop Gain vs. Output Voltage Headroom vs. Power Supply. 21668A-page 6 2002 Microchip Technology Inc. MCP6141/2/3/4 Note: Unless otherwise indicated, VDD = +5V, VSS = GND, TA = 25C, VCM = VDD/2, RL = 1 M to VDD/2, CL = 60 pF, and VOUT ~ V DD/2. Channel-to-Channel Separation (dB) 140 130 120 110 100 Input-Referred 90 1k 1000 Frequency (Hz) 10k 10000 Gain Bandwidth Product (kHz) 180 160 140 120 100 80 60 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -0.5 Common Mode Input Voltage (V) 5.5 90 Gain Bandwidth Product 75 60 Phase Margin 45 30 VDD = 1.4 V CL = 60 pF -40 -20 0 20 40 60 Ambient Temperature (C) 80 15 0 Phase Margin () Gain Bandwidth Product 60 50 40 30 20 10 0 FIGURE 2-19: Channel to Channel Separation vs. Frequency (MCP6142 and MCP6144 only). 120 Gain Bandwidth Product (kHz) 100 80 60 40 20 0 -40 -20 0 20 40 60 80 Ambient Temperature (C) VDD = 5.5 V Phase Margin 90 75 60 45 30 15 0 Phase Margin () FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. Gain Bandwidth Product 120 Gain Bandwidth Product (kHz) 100 80 60 40 20 0 FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V. 12 Closed Loop Gain Frequency (kHz) 10 8 6 4 2 0 G = +10 V/V VDD = 5.5 V 0.00 100p Load Capacitance (F) Phase Margin 90 Phase Margin () 75 60 45 30 15 0 0.00 1n FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 1.4V. 40 35 30 25 20 15 10 5 0 -40 -20 0 20 40 60 80 Ambient Temperature (C) +ISC, VDD = 1.4 V -ISC, VDD = 1.4 V -ISC, VDD = 5.5 V +ISC, VDD = 5.5 V Closed Loop Gain Frequency 0.00 10p FIGURE 2-21: Closed Loop Gain Frequency, Phase Margin vs. Load Capacitance with VDD = 5.5V. FIGURE 2-24: Output Short Circuit Current vs. Ambient Temperature vs. Power Supply Voltage. 2002 Microchip Technology Inc. Output Short Circuit Current (pA) 21668A-page 7 Phase Margin () Phase Margin 90 80 70 MCP6141/2/3/4 Note: Unless otherwise indicated, VDD = +5V, VSS = GND, TA = 25C, VCM = VDD/2, RL = 1 M to VDD/2, CL = 60 pF, and VOUT ~ V DD/2. 50 45 40 35 30 25 20 15 10 5 0 -40 -20 10 VDD = 5.5 V Falling Edge Output Voltage Swing (VP-P) Slew Rate (V/ms) 1 VDD = 1.4 V Rising Edge 0 20 40 60 Ambient Temperature (C) 80 0.1 100 100 1k 1000 Frequency (Hz) 10k 10000 FIGURE 2-25: Temperature. Output Voltage Headroom (mV) 1,000 Slew Rate vs. Ambient FIGURE 2-28: Output Voltage Swing vs. Frequency vs. Power Supply Voltage. 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -40 -20 0 20 40 60 Ambient Temperature (C) 80 Output Voltage Headroom (mV) VDD = 5.5 V RL = 50 k 100 VOL-VSS, VDD = 1.4 V VOL - VSS 10 VOL-VSS, VDD = 5.5 V VDD - VOH 1 1.E-05 10 1.E-04 100 1.E-03 1m 1.E-02 10m Output Current Magnitude (A) FIGURE 2-26: Output Voltage Headroom vs. Output Current Magnitude vs. Power Supply Voltage. 0.08 FIGURE 2-29: Output Voltage Headroom vs. Ambient Temperature with VDD = 5.5V. 0.08 Output Voltage (20 mV/div) Output Voltage (20 mV/div) 0.06 G = +11 V/V RL = 50 k 0.06 G = -10 V/V RF = 50 k 0.04 0.04 0.02 0.02 0.00 0.00 -0.02 -0.02 -0.04 -0.04 -0.06 -0.06 -0.08 0.E+00 1.E-04 2.E-04 3.E-04 4.E-04 5.E-04 6.E-04 7.E-04 8.E-04 9.E-04 1.E-03 -0.08 0.E+00 1.E-04 2.E-04 3.E-04 4.E-04 5.E-04 6.E-04 7.E-04 8.E-04 9.E-04 1.E-03 Time (100 s/div) Time (100 s/div) FIGURE 2-27: Small Signal Non-Inverting Pulse Response vs. Time. FIGURE 2-30: Small Signal Inverting Pulse Response vs. Time. 21668A-page 8 2002 Microchip Technology Inc. MCP6141/2/3/4 Note: Unless otherwise indicated, VDD = +5V, VSS = GND, TA = 25C, VCM = VDD/2, RL = 1 M to VDD/2, CL = 60 pF, and VOUT ~ V DD/2. 5.0 4.5 Output Voltage (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.E+00 2.E-04 4.E-04 6.E-04 8.E-04 1.E-03 1.E-03 1.E-03 2.E-03 2.E-03 2.E-03 G = +11 V/V RL = 50 k Output Voltage (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.E+00 2.E-04 4.E-04 6.E-04 8.E-04 1.E-03 1.E-03 1.E-03 G = -10 V/V RF = 50 k 2.E-03 2.E-03 2.E-03 Time (200 s/div) Time (200 s/div) FIGURE 2-31: Large Signal Non-Inverting Pulse Response vs. Time. 27.5 25.0 22.5 20.0 17.5 15.0 12.5 10.0 7.5 5.0 2.5 0.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 FIGURE 2-34: Large Signal Inverting Pulse Response vs. Time. 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 VOUT on G = +11 V/V V IN = 3.0 V VOUT on VOUT on Hysteresis CS swept high to low CS swept low to high VOUT HI-Z G = +11 V/V VIN = 3.0 V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Chip Select Voltage (V) Chip Select Voltage (V) VOUT Hi-Z CS Voltage 0.E+00 1.E-03 2.E-03 3.E-03 4.E-03 5.E-03 6.E-03 7.E-03 8.E-03 9.E-03 1.E-02 Time (1 ms/div) FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6143 only). 6 Input, Output Voltages (V) 5 4 3 2 1 0 -1 0.E+00 5.E-03 1.E-02 2.E-02 2.E-02 3.E-02 Output Voltage (V) FIGURE 2-35: Output Voltage vs. Chip Select (CS) Voltage (MCP6143 only). G = +11 V/V VIN VOUT Time (5 ms/div) FIGURE 2-33: The MCP6141/2/3/4 family shows no phase reversal (for information only- the Maximum Absolute Input Voltage is still VSS - 0.3V and VDD + 0.3V). 2002 Microchip Technology Inc. Output Voltage (V) 21668A-page 9 MCP6141/2/3/4 3.0 APPLICATIONS INFORMATION 3.3 Rail-to-Rail Output The MCP6141/2/3/4 family of operational amplifiers are fabricated on Microchip's state-of-the-art CMOS process. They are stable for noise gain of 10 V/V or higher. Microchip also produces a unity gain stable product, the MCP6041/2/3/4 family, which has similar specifications. The MCP6041/2/3/4 family has a bandwidth of 1.4 kHz at a noise gain of 10 V/V, while the MCP6141/2/3/4 family has a bandwidth of 10 kHz at a noise gain of 10 V/V. These devices are suitable for a wide range of applications requiring very low power consumption. With these op amps, the power supply pin needs to be bypassed with a 0.1 F capacitor. The MCP6141/2/3/4 family Maximum Output Voltage Swing defines the maximum swing possible under a particular output load. According to the specification table, the output can reach up to 10 mV of either supply rail with a 50 k load. 3.4 Input Voltage and Phase Reversal The MCP6141/2/3/4 op amp family uses CMOS transistors at the input. It is designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 2-33 shows an input voltage exceeding both supplies without output phase reversal. The maximum operating VCM that can be applied to the inputs is VSS -0.3V and VDD + 0.3V. Voltage on the input that exceeds this absolute maximum rating can cause excessive current to flow in or out of the input pins. Current beyond 2 mA can cause possible reliability problems. Applications that exceed this rating must be externally limited with an input resistor, as shown in Figure 3-1. 3.1 Rail-to-Rail Input The input stage of these devices uses two differential input stages in parallel; one operates at low VCM (common mode input voltage) and the other at high V CM. With this topology, the MCP6141/2/3/4 family operates with VCM up to 300 mV past either supply rail. The Input Offset Voltage is measured at both VCM = VSS - 0.3V and VDD + 0.3V to ensure proper operation. 3.2 Output Loads and Battery Life RIN VIN ( Maximum expected V IN ) - V DD R IN -----------------------------------------------------------------------------2 mA V SS - ( Minimum expected V IN ) R IN --------------------------------------------------------------------------2 mA MCP614X VOUT The MCP6141/2/3/4 op amp family has low quiescent current, which supports battery-powered applications. There is minimal quiescent current glitch when chip select (CS) is raised or lowered. This prevents excessive current draw and reduced battery life when the part is turned off or on. Heavy resistive loads at the output can cause excessive battery drain. Driving a DC voltage of 2.5V across a 100 k load resistor will cause the supply current to increase by 25 A, depleting the battery 43 times as fast as IQ (0.6 A typ) alone. High frequency signals (fast edge rate) across capacitive loads will also significantly increase supply current. For instance, a 0.1 F capacitor at the output presents an AC impedance of 15.9 k (1/2fC) to a 100 Hz sinewave. It can be shown that the average power drawn from the battery by a 5.0 Vp-p sinewave (1.77 Vrms) under these conditions is: FIGURE 3-1: An input resistor, RIN, should be used to limit excessive input current if the inputs exceed the absolute maximum specification. 3.5 Stability EQUATION P SUPPLY = ( V DD - V SS ) ( I Q + V L ( p - p ) fC L ) = ( 5V ) ( 0.6A + 5.0V p - p 100Hz 0.1F ) = 3.0W + 50W This will drain the battery 18 times as fast as IQ alone. The MCP6141/2/3/4 op amp family is designed to give high bandwidth and faster slew rate for circuits with high noise (Gn) or signal gain. The related unity-gain stable MCP6041/2/3/4 op amp family has lower AC performance, but it is preferable for low noise gain applications. Noise gain is defined to be the gain from a voltage source at the non-inverting input to the output when all other voltage sources are zeroed (shorted out). Noise gain is independent of signal gain and depends only on components in the feedback loop. 21668A-page 10 2002 Microchip Technology Inc. MCP6141/2/3/4 RG RF Note that the integrator circuit in Figure 3-3 becomes unity gain at high frequencies because of the capacitor. Therefore, this circuit is unstable for the MCP6141/2/3/4. VOUT MCP614X VIN 3.6 Capacitive Load and Stability Non-inverting noise gain: 1 + RF/RG +10 V/V VIN RG RF MCP614X VOUT Driving capacitive loads can cause stability problems with voltage feedback op amps. Figure 2-21 shows how increasing the load capacitance will decrease the phase margin. While a phase margin above 60 is ideal, 45 is on the verge of instability. As can be seen, up to CL = 150 pF can be placed on the MCP6141/2/3/4 op amp outputs without any problems, while 250 pF creates a 45 phase margin. When the op amp is required to drive large capacitive loads (CL >150 pF), a small series resistor (RISO in Figure 3-4) at the output of the amplifier improves the phase margin. This resistor makes the output load resistive at higher frequencies, which improves the phase margin. The bandwidth reduction caused by the capacitive load, however, is not changed. To select RISO, start with 1 k, then use the MCP6141 SPICE macro model and bench testing to adjust RISO until there is a minimum frequency response peaking. R2 R1 RISO MCP614X VIN CL VOUT Inverting noise gain: 1 + RF/R G +10 V/V FIGURE 3-2: Noise gain for inverting and non-inverting amplifier configuration. Figure 3-2 shows non-inverting and inverting amplifier circuits. In order for the amplifiers to be stable, the noise gain should meet the specified requirement: EQUATION RF G n = 1 + ------ 10V/V RG Note that an inverting signal gain of G = -9 V/V corresponds to a noise gain G n = +10 V/V. Figure 3-3 shows a unity gain buffer and integrator that are unstable when used with the MCP6141/2/3/4 family. However, they are suitable for the MCP6041/2/3/4 family. FIGURE 3-4: capacitive loads. Amplifier circuit for heavy 3.7 MCP604X VIN Unity gain buffer: Unstable for MCP614X C VOUT The MCP6143 Chip Select (CS) Option R VIN The MCP6143 is a single amplifier with a chip select (CS) option. When CS is pulled high, the supply current drops to 20 pA (typ.) and goes through the CS pin to VSS. When this happens, the amplifier is put into a high impedance state. By pulling CS low, the amplifier is enabled. If the CS pin is left floating, the amplifier will not operate properly. Figure 3-5 shows the output voltage and supply current response to a CS pulse. MCP604X VOUT Integrator: Unstable for MCP614X FIGURE 3-3: Typical Circuits that are not suitable for the MCP6141/2/3/4 family. 2002 Microchip Technology Inc. 21668A-page 11 MCP6141/2/3/4 CS VIL tON VOUT Hi-Z 0.6 A, typ IVDD 5 pA, typ 0.6 A, typ IVSS 20 pA, typ 5 pA, typ 20 pA, typ 5 pA, typ 5 pA, typ VIH tOFF Hi-Z Circuit schematics for different guard ring implementations are shown in Figure 3-7. Figure 3-7A biases the guard ring to the input common mode voltage, which is most effective for non-inverting gains. Figure 3-7B biases the guard ring to a reference voltage (VREF, which can be ground), which is useful for inverting gains and precision photo sensing circuits. Figure 3-7A VDD MCP614X VREF Figure 3-7B ICS FIGURE 3-5: Timing Diagram for the CS function on the MCP6143 op amp. 3.8 Layout Considerations VREF VDD MCP614X Good PC board layout techniques will help you achieve the performance shown in the specifications and typical performance curves. It will also assist in minimizing Electro-Magnetic Compatibility (EMC) issues. 3.8.1 SURFACE LEAKAGE In applications where low input bias current is critical, PC board surface leakage effects and signal coupling from trace to trace need to be considered. Surface leakage is caused by a difference in voltage between traces, combined with high humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow, which is greater than the input current of the MCP6141/2/3/4 family at 25C (1 pA, typ). The simplest technique to reduce surface leakage is using a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin or trace. Figure 3-6 shows an example of a typical layout. ININ+ VSS FIGURE 3-7: Two possible guard ring connection strategies to reduce surface leakage effects. 3.8.2 COMPONENT PLACEMENT In order to help prevent crosstalk: * Separate digital components from analog components, and low speed devices from high speed devices. * Keep sensitive traces short and straight. Separate them from interfering components and traces. This is especially important for high frequency (low rise time) signals. * Use a 0.1 F supply bypass capacitor within 0.1" (2.5 mm) of the VDD pin. It must connect directly to the ground plane. Guard Ring FIGURE 3-6: layout. Example of Guard Ring 21668A-page 12 2002 Microchip Technology Inc. MCP6141/2/3/4 3.8.3 SIGNAL COUPLING 3.9 3.9.1 Typical Applications BATTERY CURRENT SENSING The input pins of the MCP6141/2/3/4 family of op amps are high impedance, which allows noise injection. This noise can be capacitively or magnetically coupled. In either case, using a ground plane helps reduce noise injection. When noise is coupled capacitively, the ground plane provides shunt capacitance to ground for high frequency signals (Figure 3-8 shows the equivalent circuit). The coupled current, IM, produces a lower voltage (VTRACE 2) on the victim trace when the trace to ground plane capacitance (C SH2) is large and the terminating resistor (RT2) is small. Increasing the distance between traces and using wider traces also helps. CM VTRACE 1 CSH1 CSH2 IM VTRACE 2 The MCP6141/2/3/4 op amps' Common Mode Input Range, which goes 300 mV beyond both supply rails, supports their use in high side and low side battery current sensing applications. The very low quiescent current (0.6 A, typ.) help prolong battery life, while the rail-to-rail output allows you to detect low currents. Figure 3-9 shows a high side battery current sensor circuit. The feedback and input resistors are sized to minimize power losses. The battery current (IDD) through the 1 k resistor causes its top terminal to be more negative than the bottom terminal. This keeps the common mode input voltage of the op amp VDD, which is within its allowed range. The output of the op amp can reach VDD - 0.1 mV (see Figure 2-26), which is a smaller error than the offset voltage. RT2 VDD VDD FIGURE 3-8: Equivalent circuit for capacitive coupling between traces on a PC board (with ground plane). When noise is coupled magnetically, the ground plane reduces the mutual inductance between traces. This occurs because the ground return current at high frequencies will follow a path directly beneath the signal trace. Increasing the separation between traces makes a significant difference. Changing the direction of one of the traces can also reduce magnetic coupling. If these techniques are not enough, it may help to place guard traces next to the victim trace. They should be on both sides of the victim trace and be as close as possible. Connect the guard traces to ground plane at both ends and in the middle for long traces. 1k +1.4 V to 5.5 V IDD 100 k MCP614X VSS 1 M FIGURE 3-9: Sensor. 3.9.2 High Side Battery Current SUMMING AMPLIFIER The rail-to-rail input and output, the 600 nA (typ.) quiescent current and the wide bandwidth make the MCP6141/2/3/4 family of operational amplifiers fit well in a summing amplifier circuit, as shown in Figure 3-10. V1 V2 V3 R1 I R2 1 I R3 2 I3 + MCP614X RF IF VOUT VREF FIGURE 3-10: Summing amplifier circuit. 2002 Microchip Technology Inc. 21668A-page 13 MCP6141/2/3/4 In this configuration, the amplifier outputs the sum of the three input voltages. The ratio of the sum and the output voltage is defined using the feedback and input resistors. V REF is used to offset the output voltage. This family of amplifiers is stable for noise gain (G n) of 10 V/ V or higher. The Gn and the signal gain of the summing amplifier is calculated as shown below: EQUATION Noise Gain: 1 1 1 G n = 1 + R F ----- + ----- + ----- 10 V/V R 1 R 2 R 3 Signal Gain: -RF V 01 = --------- x V 1 R1 -RF V 02 = --------- x V 2 R2 -RF V 03 = --------- x V 3 R3 RF RF RF V 04 = 1 + ------ + ------ + ------ x V REF R 1 R 2 R 3 V OUT = V 01 + V 02 + V 03 + V 04 VOUT V - V 1 V REF - V 2 V REF - V 3 REF = R F ---------------------- + ---------------------- + ---------------------- + V REF R R R 1 2 3 At a noise gain of 10 V/V, the amplifier bandwidth is approximately 10 kHz. The bandwidth to quiescent current ratio of MCP6141/2/3/4 makes this device an appropriate choice for battery-powered applications. 21668A-page 14 2002 Microchip Technology Inc. MCP6141/2/3/4 4.0 SPICE MACRO MODEL The Spice macro model for the MCP6141, MCP6142, MCP6143 and MCP6144 simulates the typical amplifier performance of offset voltage, DC power supply rejection, input capacitance, DC common mode rejection, open loop gain over frequency, phase margin, output swing, DC power supply current, power supply current change with supply voltage, input common mode range, output voltage range vs. load and input voltage noise. The characteristics of the MCP6141, MCP6142, MCP6143 and MCP6144 amplifiers are similar in terms of performance and behavior. This single op amp macro model supports all four devices, with the exception of the chip select function of the MCP6143, which is not modeled. The listing for this macro model is shown on the next page. The most recent revision of the model can be downloaded from Microchip's web site at www.microchip.com. 2002 Microchip Technology Inc. 21668A-page 15 MCP6141/2/3/4 Software License Agreement The software supplied herewith by Microchip Technology Incorporated (the "Company") is intended and supplied to you, the Company's customer, for use solely and exclusively on Microchip products. The software is owned by the Company and/or its supplier, and is protected under applicable copyright laws. All rights are reserved. Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws, as well as to civil liability for the breach of the terms and conditions of this license. THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. .SUBCKT MCP6141 1 2 3 4 5 * ||||| * | | | | Output * | | | Negative Supply * | | Positive Supply * | Inverting Input * Non-inverting Input * * Macromodel for the MCP6141/2/3/4 op amp family: * MCP6141 (single) * MCP6142 (dual) * MCP6143 (single w/ CS; chip select is not modeled) * MCP6144 (quad) * * Revision History: * REV A: 06-Sep-02, KEB (created model) * * Recommendations: * Use PSPICE (or SPICE 2G6; other simulators may require translation) * For a quick, effective design, use a combination of: data sheet * specs, bench testing, and simulations with this macromodel * For high impedance circuits, set GMIN=100F in the .OPTIONS * statement * * Supported: * Typical performance at room temperature (25 degrees C) * DC, AC, Transient, and Noise analyses. * Most specs, including: offsets, DC PSRR, DC CMRR, input impedance, * open loop gain, voltage ranges, supply current, ... , etc. * * Not Supported: * Chip select (MCP6143) * Variation in specs vs. Power Supply Voltage * Distortion (detailed non-linear behavior) * Temperature analysis * Process variation * Behavior outside normal operating region * * Input Stage V10 3 10 -300M R10 10 11 258K R11 10 12 258K C11 11 12 3.53P C12 1 0 6.00P E12 1 14 POLY(4) 20 0 21 0 26 0 27 0 1.00M 117 117 1 1 I12 14 0 1.50P M12 11 14 15 15 NMI L=2.00U W=5.00U C13 14 2 6.00P M14 12 2 15 15 NMI L=2.00U W=5.00U I14 2 0 500E-15 C14 2 0 6.00P 2002 Microchip Technology Inc. 21668A-page 16 MCP6141/2/3/4 I15 15 4 300N V16 16 4 200M D16 16 15 DL V13 3 13 50.0M D13 14 13 DL * * Noise, PSRR, and CMRR I20 21 20 423U D20 20 0 DN1 D21 0 21 DN1 G26 0 26 POLY(1) 3 4 308U -56.0U R26 26 0 1 G27 0 27 POLY(2) 1 3 2 4 -979U 178U 178U R27 27 0 1 * * Open Loop Gain, Slew Rate G30 0 30 POLY(1) 12 11 0 1.00K R30 30 0 1 E31 31 0 POLY(1) 3 4 29.3 1.05 D31 30 31 DL E32 0 32 POLY(1) 3 4 57.0 2.04 D32 32 30 DL G33 0 33 POLY(1) 30 0 0 562 R33 33 0 1 C33 33 0 838M G34 0 34 POLY(1) 33 0 0 1.00 R34 34 0 1.00 C34 34 0 8.53U G35 0 35 POLY(2) 34 0 33 34 0 1.00 1.22 R35 35 0 1.00 * * Output Stage G50 0 50 POLY(1) 57 5 0 1.00 D51 50 51 DL R51 51 0 1K D52 52 50 DL R52 52 0 1K G53 3 0 POLY(1) 51 0 300N 1M G54 0 4 POLY(1) 52 0 300N -1M E55 55 0 POLY(2) 3 0 51 0 -10M 1 -100M D55 57 55 DLS E56 56 0 POLY(2) 4 0 52 0 10M 1 -100M D56 56 57 DLS G57 0 57 POLY(3) 3 0 4 0 35 0 0 17.8U 17.8U 35.5U R57 57 0 28.2K R58 57 5 1.00 C58 5 0 2.00P * * Models .MODEL NMI NMOS .MODEL DL D N=1 IS=1F .MODEL DLS D N=10M IS=1F .MODEL DN1 D IS=1F KF=1.17E-18 AF=1 * .ENDS MCP6141 2002 Microchip Technology Inc. 21668A-page 17 MCP6141/2/3/4 5.0 5.1 PACKAGING INFORMATION Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Example: MCP6141 I/P058 0223 8-Lead SOIC (150 mil) Example: MCP6142 I/SN0223 058 XXXXXXXX XXXXYYWW NNN 8-Lead MSOP XXXXXX YWWNNN Example: 6143I 223058 Legend: XX...X YY WW NNN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. 21668A-page 18 2002 Microchip Technology Inc. MCP6141/2/3/4 5.1 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP6144) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN MCP6144-I/P 0223058 14-Lead SOIC (150 mil) (MCP6144) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN MCP6144ISL 0223058 14-Lead TSSOP (MCP6144) Example: XXXXXX YYWW NNN 6144ST 0223 058 2002 Microchip Technology Inc. 21668A-page 19 MCP6141/2/3/4 8-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A A2 c L A1 eB B1 p B Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB MIN INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10 MAX MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 .170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 21668A-page 20 2002 Microchip Technology Inc. MCP6141/2/3/4 8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A A2 L A1 Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX MIN .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 2002 Microchip Technology Inc. 21668A-page 21 MCP6141/2/3/4 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) p E E1 D 2 B n 1 A c A1 A2 (F) L Units Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Footprint (Reference) Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom *Controlling Parameter Significant Characteristic Notes: Dimension Limits n p A A2 A1 E E1 D L F c B .030 .002 .184 .114 .114 .016 .035 0 .004 .010 MIN INCHES NOM 8 .026 .044 .034 .193 .118 .118 .022 .037 .006 .012 7 7 .038 .006 .200 .122 .122 .028 .039 6 .008 .016 MAX MIN MILLIMETERS* NOM 0.65 1.18 0.76 0.05 4.67 2.90 2.90 0.40 0.90 0 0.10 0.25 0.15 0.30 7 7 4.90 3.00 3.00 0.55 0.95 0.86 0.97 0.15 .5.08 3.10 3.10 0.70 1.00 6 0.20 0.40 MAX 8 Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. Drawing No. C04-111 21668A-page 22 2002 Microchip Technology Inc. MCP6141/2/3/4 14-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A A2 c eB A1 B1 B p L Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MIN MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 2002 Microchip Technology Inc. 21668A-page 23 MCP6141/2/3/4 14-Lead Plastic Small Outline (SL) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A A2 Units Dimension Limits n p A A2 A1 E E1 D h L c B L A1 MIN Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic .053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0 INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MAX MIN .069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15 MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 MAX 1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 21668A-page 24 2002 Microchip Technology Inc. MCP6141/2/3/4 14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP) E E1 p D 2 n B 1 A c L A1 A2 Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L c B1 MIN INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5 MAX MIN .033 .002 .246 .169 .193 .020 0 .004 .007 0 0 .043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 2002 Microchip Technology Inc. 21668A-page 25 MCP6141/2/3/4 NOTES: 21668A-page 26 2002 Microchip Technology Inc. MCP6141/2/3/4 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape(R) or Microsoft(R) Internet Explorer. Files are also available for FTP download from our FTP site. SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events 092002 2002 Microchip Technology Inc. DS21668A-page 27 MCP6141/2/3/4 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: MCP6141/2/3/4 Questions: 1. What are the best features of this document? Y N Literature Number: DS21668A FAX: (______) _________ - _________ 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21668A-page 28 2002 Microchip Technology Inc. MCP6141/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package Examples: a) b) Device: MCP6141: CMOS Single Op Amp MCP6141T: CMOS Single Op Amp (Tape and Reel for SOIC, MSOP) MCP6142: CMOS Dual Op Amp MCP6142T: CMOS Dual Op Amp (Tape and Reel for SOIC and TSSOP) MCP6143: CMOS Single Op Amp w/CS Function MCP6143T: CMOS Single Op Amp w/CS Function (Tape and Reel for SOIC and MSOP) MCP6144: CMOS Quad Op Amp MCP6144T: CMOS Quad Op Amp (Tape and Reel for SOIC and TSSOP) I MS P SN SL ST = -40C to +85C = = = = = Plastic MSOP, 8-lead Plastic DIP (300 mil Body), 8-lead, 14-lead Plastic SOIC (150 mil Body), 8-lead Plastic SOIC (150 mil Body), 14-lead Plastic TSSOP (4.4mm Body), 14-lead MCP6141-I/P: PDIP package. Industrial temperature, MCP6141T-I/SN: Tape and Reel, Industrial temperature, SOIC package. MCP6142-I/SN: SOIC package. MCP6142-I/MS: MSOP package. MCP6143-I/MS: MSOP package. MCP6143-I/P: PDIP package. MCP6144-I/SL: SIOC package. Industrial Industrial temperature, temperature, a) b) a) b) a) b) Industrial Industrial Industrial temperature, temperature, temperature, Temperature Range: Package: MCP6144T-I/ST: Tape and Reel, Industrial temperature, TSSOP package. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2002 Microchip Technology Inc. DS21668A-page 29 MCP6141/2/3/4 NOTES: DS21668A-page 30 2002 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro (R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. 2002 Microchip Technology Inc. DS21668A - page 31 M WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com ASIA/PACIFIC Australia Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Japan Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Rocky Mountain 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-4338 China - Beijing Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Atlanta 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Boston 2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821 China - Chengdu Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599 Taiwan Microchip Technology (Barbados) Inc., Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 Chicago 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas 4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924 China - Fuzhou Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521 Detroit Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 EUROPE Austria Microchip Technology Austria GmbH Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 China - Shanghai Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 Kokomo 2767 S. Albright Road Kokomo, Indiana 46902 Tel: 765-864-8360 Fax: 765-864-8387 Denmark Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 Los Angeles 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 China - Shenzhen Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1315, 13/F, Shenzhen Kerry Centre, Renminnan Lu Shenzhen 518001, China Tel: 86-755-2350361 Fax: 86-755-2366086 New York 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335 France Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 China - Hong Kong SAR Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Germany Microchip Technology GmbH Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 India Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 Italy Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 08/01/02 DS21668A-page 32 2002 Microchip Technology Inc. |
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